Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization

Logic resynthesis is one of the core problems in modern peephole logic optimization algorithms. Given a target function and set existing functions, asks for circuit reusing some functions generating target. While exact methods such as enumeration SATbased synthesis guarantee optimal solutions, limitations on problem size are inevitable due to scalability concerns. In this work, we propose heuristic algorithms ANDbased, majority-based, multiplexer-based circuits, which scalable all aspects. Used high-effort optimization, our play key role enabling 2-3% further reduction benchmarks that already processed by state-of-the-art flows.